// 寄存器

module Regfile (
    input [2:0] ra,rb,rc,wn,
    input [15:0] d,
    input RST,wreg,clk,
    output wire [15:0] qa,qb,qc
);

    reg [15:0] register [7:1];

    localparam  
                R1 = 3'b001,
                R2 = 3'b010,
                R3 = 3'b011,
                R4 = 3'b100,
                R5 = 3'b101,
                R6 = 3'b110,
                R7 = 3'b111;

    assign qa = (ra == 3'b000) ? 0:register[ra];
    assign qb = (rb == 3'b000) ? 0:register[rb];
    assign qc = (rc == 3'b000) ? 0:register[rc];

    always @(posedge clk) begin
        if (RST == 1'b1) begin
            register[R1] <= {16{1'b0}};
            register[R2] <= {16{1'b0}};
            register[R3] <= {16{1'b0}};
            register[R4] <= {16{1'b0}};
            register[R5] <= {16{1'b0}};
            register[R6] <= {16{1'b0}};
            register[R7] <= {16{1'b0}};
        end
        else begin
            if (wn != 3'b000 & wreg == 1'b1) begin
                register[wn] <= d;
            end 
        end
    end
    
endmodule